Architectural Patterns in Mobile CPUs for Balancing Power, Performance, and Area (PPA)
Keywords:
Mobile CPUs, Power Efficiency, Area Minimization, System-on-Chip (SoC), Architectural Patterns, Big.LITTLE, PPA MetricsAbstract
This paper aims to survey various existing architecture patterns for mobile CPUs in light of power consumption, performance, and chip size considerations. The paper focuses on the approaches to measuring PPA, including the provision of benchmark tests and simulations along with PPA analysis in case studies with real-world applications. Thus, by describing the continued development of the Big.LITTLE architecture and reviewing current innovations such as machine learning-based workload control for mobile CPU design, this paper helps identify development trends. It is then followed by an evaluation of the simulation results and real-life studies before looking at the results and stressing how interdisciplinary is very important in solving this ever-increasing problem of efficiency and high-performance mobile computing systems.
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Copyright (c) 2025 Vinay Panchal (Author)
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