DESIGN AND IMPLEMENTATION OF LOW POWER PIPELINED FFT ARCHITECTURE FOR DSP APPLICATION
Keywords:
Fast Fourier Transform, Radix-2 Butterfly, Pipelining Technique, Clock GatingAbstract
The swift advancements in signal analysis applications have heightened the need for efficient, high-performance architectures to execute complex algorithms like the Quick Fourier Transform (FFT). This study introduces a VLSI implementation of a pipelined FFT architecture customized for DSP applications, addressing challenges in real-time processing, power consumption, and resource utilization. By exploiting the parallelism of the FFT algorithm and using pipelining techniques, our design achieves high throughput and low latency with minimal area overhead and power consumption. Implemented through VLSI techniques, this architecture can be integrated into dedicated DSP processors or system-on-chip (SoC) designs. It is optimized for area efficiency, making it suitable for resource-constrained applications while maintaining high performance. Extensive simulations and comparisons with existing FFT architectures demonstrate its superior throughput, latency, and power efficiency. Additionally, clock gating strategies are employed to further reduce power consumption. The design, synthesized using Xilinx tools and implemented on an Artix-7 FPGA board, was verified for theoretical accuracy using Verilog HDL
References
M. Garrido, J. Grajal, M. A. Sanchez, and O. Gustafsson, “Pipelined radix-2k Feed forward FFT Architectures,” IEEE Transactions on Very Large-Scale Integration (VLSI) Systems, vol. 21, no. 1, pp. 23–32, 2013.
H. M. Saleh and E. Swartzlander, “FFT Implementation with Fused Floating-Point Operations”, IEEE Transactions on Computers, No. 2, Vol. 61, February 2012, pp. 284 – 288.
M Jaber and D. Massicotte “Radix-2α/4βBuilding Blocks for Efficient VLSI’s Higher Radices Butterflies Implementation," VLSI Design, vol. 2014, Article ID 690594, 13 pages, 2014.
Jung. Y, Yoon. H, Kim. J, «New Efficient FFT Algorithm Pipeline Implementation Results OFDM/DMT Applications», IEEE Transaction on Consumer Electronics, Vol. 49, No. 1, pp.14-20, February 2003.
J. A. Johnston, “Parallel pipeline fast Fourier transformer,” IEE Proceedings F: Communications, Radar and Signal Processing,vol. 130, no. 6, pp. 564–572, 1983.
M. Garrido, S.-J. Huang, and S.-G. Chen, “Feedforward FFT hardware architectures based on rotator allocation,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 65, no. 2, pp. 581–592, Feb. 2018.
M. Garrido, J. Grajal, M. A. Sanchez, and O. Gustafsson, “Pipelined radix-2k feedforward FFT architectures,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 21, no. 1, pp. 23–32, Jan. 2013.
N. Li and N. P. van der Meijs, “A radix 22 based parallel pipeline FFT processor for MB-OFDM UWB system,” in Proc. IEEE Int. SOC Conf. (SOCC), Sep. 2009, pp. 383–386.
ManoharAyinala, Keshab K. Parhi, ”Parallel-Pipelined Radix-22 FFT Architecture for Real Valued Signals”, Conference Record of the Forty Fourth Asilomar Conference on Signals, Systems and Computers,7-10 Nov,2010.
G. Paim, H. Amrouch, E. A. C. D. Costa, S. Bampi, and J. Henkel, “Bridging the gap between voltage over-scaling and joint hardware accelerator-algorithm closed-loop,” IEEE Trans. Circuits Syst. Video Technol., vol. 32, no. 1, pp. 398–410, Jan. 2022.
B. Moons, D. Bankman, L. Yang, B. Murmann, and M. Verhelst, “BinarEye: An always-on energy-accuracy-scalable binary CNN processor with all memory on chip in 28 nm CMOS,” inProc. IEEE Custom Integr. Circuits Conf. (CICC), Apr. 2018, pp. 1–4.
ManoharAyinala, Member, IEEE, and Keshab K. Parhi, Fellow, IEEE, “FFT Architecture for Real-Valued Signals Based on Radix-23 and Radix-24 Algorithms”, IEEE Transactions on Cir and Sys-I: Regular Papers.
G. Paim et al., “On the resiliency of NCFET circuits against voltage over-scaling,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 68, no. 4, pp. 1481–1492, Apr. 2021.
KodakandlaAbhilash and P.Reena Monica,” FFT Architectures for Real Valued Signals based Different Radices Algorithm”, Indian Journal of Science and Technology, Vol8(20), DOI:10.17485/ijst/2015/ v8i20/78462, August 2015.
N. Li and N. P. van der Meijs, “A radix 22 based parallel pipeline FFT processor for MB-OFDM UWB system,” in Proc. IEEE Int. SOC Conf. (SOCC), Sep. 2009, pp. 383–386.
D. Wold, “Pipeline and parallel-pipeline FFT processors for VLSI implementations,” IEEE Trans. Comput., vol. C-33, no. 5, pp. 414–426, May 1984.
S.-I. Cho, K.-M. Kang, and S.-S. Choi, “Implemention of 128-point fast Fourier transform processor for UWB systems,” in Proc. Int. Wireless Commun. Mobile Comput. Conf., Aug. 2008, pp. 210–213.
M. Garrido, J. Grajal, M. A. Sanchez, and O. Gustafsson, “Pipelined radix-2k feedforward FFT architectures,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 21, no. 1, pp. 23–32, Jan. 2013.
M. Garrido, M. Acevedo, A. Ehliar, and O. Gustafsson, “Challenging the limits of FFT performance on FPGAs (Invited paper),” in Proc. Int. Symp. Integr. Circuits (ISIC), Dec. 2014, pp. 172–175.
T. Ahmed, M. Garrido, and O. Gustafsson, “A 512-point 8-parallel pipelined feedforward FFT for WPAN,” in Proc. Conf. Rec. 45th Asilomar Conf. Signals, Syst. Comput. (ASILOMAR), Nov. 2011, pp. 981–984.
M. Garrido, S.-J. Huang, S.-G. Chen, and O. Gustafsson, “The serial commutator FFT,” IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 63, no. 10, pp. 974–978, Oct. 2016.
S.-C. Hsu, S.-J. Huang, S.-G. Chen, S.-C. Lin, and M. Garrido, “A 128- point multi-path SC FFT architecture,” in Proc. IEEE Int. Symp. Circuits Syst. (ISCAS), Oct. 2020, pp. 1–5.
Downloads
Published
Issue
Section
License
Copyright (c) 2024 Swati Kumari Roy, Vijaya Prakash A.M (Author)
This work is licensed under a Creative Commons Attribution-NonCommercial 4.0 International License.
