LOW POWER HIGH SPEED HANS CARLSON ADDER USING SPST
Abstract
The concept of SPST is to segregate the arithmetic units into Most significant Part (MSP) & Least significant Part (LSP), where MSP doesn’t affect most of computation results. Efficient adders are beneficial in the arithmetic circuit design. Ripple carry adder was found to have lowest gate count but maximum delay. To address the area and delay, a high speed low power Han Carlson adder adopting SPST is proposed in this part of process. Hans Carlson adder’s is coalescence of two designs comprising Kogge-stone and the Brent-Kung construction. The Xilinx- Vivado tool was used to simulate the results. In contrast with the other SPST adders, the proposed SPST Han Carlson Adder’s has a lower delay imbibing of 450ps and an area of 7 cells or area.
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Copyright (c) 2024 Veena M B, Nikitha M , Soundarya N (Author)
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